Parallelizable, scalable, fault-tolerant multi-qubit Parity gates

Innsbruck, 18.12.2025  – A group of physicists at ParityQC have introduced a new method to implement efficient, fault-tolerant logical multi-qubit gates with the ParityQC Architecture. The findings are detailed in a new pre-print, “Fault-tolerant multi-qubit gates in Parity Codes”.

A major challenge in current quantum computing architectures is the difficulty of performing logical operations between distant qubits, as well as the parallelizability of such logical interactions. Standard approaches often require complex “lattice surgery” or significant overhead to move information across the chip, which limits the speed and depth of quantum algorithms.

In the new paper “Fault-tolerant multi-qubit gates in Parity Codes”, a group of physicists at ParityQC (Anette Messinger, Christophe Goeller and Wolfgang Lechner) demonstrates that Parity Codes can bypass these limitations. By leveraging the specific structure of Parity Qubits, the physicists show how to perform logical long-range entangling gates by only acting locally on the code.

The authors present a set of logical gates that are efficiently implementable within concatenated quantum error correction codes. Key innovations include:

• Arbitrary Angle Rotations: The ability to perform fault-tolerant high-weight rotation gates of arbitrary angles on single physical qubits or localized regions.
• Parity-Controlled-NOT Gates: The implementation of logical parity-controlled-NOT operations between arbitrarily many logical qubits using transversal CNOT gates.
• No Lattice Surgery Required: Unlike conventional approaches, these operations can be implemented and often parallelized without the need for lattice surgery or complicated routing operations.

A defining feature of the new method is how it reimagines the role of “redundancy” in error correction. In the ParityQC Architecture, the qubits added for error protection act to increase redundancy and enable logical connectivity at the same time.

By keeping the redundancy of the Parity Code in a single basis, the Architecture allows the system to address the same logical qubit on different physical qubits simultaneously without violating the no-cloning theorem. This unique property enables the creation of parallelizable logical multi-qubit gates, a promising route toward scalable quantum computing that avoids the bottlenecks of traditional routing.

Error correction with the ParityQC Architecture

The ParityQC Architecture enables long-range entangling gates using solely local operations, thus supporting an efficient and scalable implementation of complex quantum algorithms. As instances of classical linear codes, Parity Codes provide intrinsic protection against specific types of quantum noise, such as bit-flip or phase-flip errors. This makes the Architecture particularly powerful when concatenated with asymmetric codes or implemented on noise-biased systems, enabling efficient fault-tolerant quantum computation.

A unified path to early fault tolerance

“This work is an important step forward for our company, further positioning the ParityQC Architecture as a promising route toward scalable, fault-tolerant quantum computing” says Wolfgang Lechner, founder of ParityQC and co-author of the paper. “We are providing a blueprint that allows hardware developers to build machines that can handle complex operations while keeping the error correction overhead manageable”.

The paper “Fault-tolerant multi-qubit gates in Parity Codes” , authored by Anette Messinger, Christophe Goeller and Wolfgang Lechner, is now available for peer review and the pre-print can be accessed here.