The ParityQC Architecture is the generalized version of the LHZ architecture for both digital and analog quantum computers. This technology harnesses a groundbreaking quantum architecture with resonance in both the academic and the corporate world. The original paper outlining this discovery was cited over 150 times and triggered research for implementations, applications and generalizations from research groups and companies all around the world. Hardware developers’ interest in the architecture stems from its scalability as well as its compatibility with current methods and platforms.

The ParityQC Architecture provides a fundamentally new way to encode optimization problems on quantum computers, defining both the hardware layout and the algorithms. While it is common practice to translate optimization problems to algorithms, whereby gates between qubits have to be programmed, the ParityQC Architecture differentiates itself by only requiring to program local fields acting on individual qubits.

Another advantage of our approach is that the gates between qubits are entirely independent of the problem. This contrasts with the traditional quantum computer, where gates act between any two qubits. In the ParityQC Architecture, gates act between four qubits, and these gates only exist between the qubits’ nearest neighbours on a 2D chip layout.