PARITYQC

Architecture

The ParityQC Architecture is the generalized version of the LHZ architecture for both digital and analog quantum computers. This technology harnesses a groundbreaking quantum architecture with resonance in both the academic and the corporate world. The original paper outlining this discovery was cited over 150 times and triggered research for implementations, applications and generalizations from research groups and companies all around the world. Hardware developers’ interest in the architecture stems from its scalability as well as its compatibility with current methods and platforms.

The ParityQC Architecture provides a fundamentally new way to encode optimization problems on quantum computers, defining both the hardware layout and the algorithms. While it is common practice to translate optimization problems to algorithms, whereby gates between qubits have to be programmed, the ParityQC Architecture differentiates itself by only requiring to program local fields acting on individual qubits.

Another advantage of our approach is that the gates between qubits are entirely independent of the problem. This contrasts with the traditional quantum computer, where gates act between any two qubits. In the ParityQC Architecture, gates act between four qubits, and these gates only exist between the qubits’ nearest neighbours on a 2D chip layout.

Reduced Complexity

Building quantum computers is a difficult task. By reducing the complexity of the architecture, the demands on the hardware structure are greatly simplified. This results in a decisive time advantage in the quest for an operational quantum computer. In the most ideal version, the chip consists only of qubits (the white dots in the icon) and interactions between their four nearest neighbours (the red squares). In addition, when building with the ParityQC architecture, algorithms get simplified as well. Currently, the complexity of the problem is encoded in gates between qubits, but with our approach, the problem will be encoded in the local fields of the qubits only. This allows for the design of much simpler algorithms.

One Chip For Every Problem

In our architecture, the interactions are independent of the problem. The problem is therefore transferred to the software rather than implemented in the hardware. By separating the problem (from the hardware), we are able to solve any optimization problem with the same chip. We do not restrict the meaning of optimization problems to combinatorial optimization only, but also include material simulation, machine learning, quantum chemistry and their manyfold applications in the real world.

All Methods and Platforms

The ParityQC Architecture is compatible with all currently available qubit platforms and can offer advantages for every type of hardware manufacturer. The architecture provides a fundamental new set of possibilities for the development of algorithms. It effectively functions as a translator of the optimization problem, independently from the algorithm, which means it is suitable for both digital and quantum annealing applications.

Scalability through Parallelizability

A significant advantage for digital applications is the complete parallelizability of the quantum gates. Full parallelizability enables constant depth algorithms, a new paradigm in quantum computing. This is a critical factor for the scalability of quantum computers and the great strength of our approach in the long- and medium-term. By introducing parallelizable gates, it is possible to eliminate unwanted cross-talk between qubits. For quantum annealing, we can implement additional quantum algorithmic building blocks (e.g. counter-diabatic driving) that are challenging traditional methods.

Qubit Control

The technological bottleneck of scalable quantum systems is not the amount of qubits, but instead how these qubits are controlled. Due to its ability to parallelize gates, the ParityQC Architecture introduces algorithms based on global gates. In each step, a pattern of gates are executed at the same time. This removes the need to implement a control signal for each individual gate and only requires ONE single control signal for all gates instead. This provides a huge advantage for the hardware design and a route to mitigate cross-talk errors during qubit design.