The ParityQC Architecture provides a fundamentally new way to program optimization problems

ParityQC provides a fundamentally new way to program optimization problems on quantum computers and to define hardware layout as well as algorithms. While it is common practice to translate optimization problems to algorithms, where gates between qubits have to be programmed, the ParityQC Architecture differentiates itself by solely programming local fields on individual qubits. 

In our approach, the gates between qubits are entirely independent of the problem. This contrasts with the traditional quantum computer, where gates act between any two qubits, by allowing gates to act between four qubits. These gates only exist between the qubits nearest neighbors on a 2D chip layout. By reducing the complexity of the architecture, the demands on the hardware structure are greatly simplified. This results in a decisive time advantage in the quest for an operational quantum computer. The ParityQC Architecture is compatible with all currently available qubit platforms, enabling us to offer advantages for every type of hardware manufacturer.

The architecture also offers a fundamental new set of possibilities for the development of algorithms. It functions as a translation of the optimization problem, independently from an algorithm and thus is compatible with both digital and quantum annealing applications. 

A significant advantage for digital applications is the complete parallelizability of the quantum gates. This is a critical factor for the scalability of quantum computers and the great strength of our approach in the long and medium term. For quantum annealing, our architecture offers additional quantum effects (e.g. counter-diabatic driving) that were not possible using traditional methods. 

Learn more about the LHZ Scheme

LHZ Architecture for quantum computing