From NISQ to Fault-Tolerance: Applications and Algorithmic Benchmarks for Spin Qubits
September 30, 2026
Hamburg / Innsbruck, 30.09.2026 – A group of researchers at ParityQC and the University of Innsbruck has charted a detailed path for running quantum algorithms on exchange-only spin qubits, spanning the full arc from today’s noisy devices to fault-tolerant quantum simulation, and shows that the Parity Twine compilation method is a natural fit for this emerging hardware platform.
The challenge: mapping algorithms to spin qubit hardware
Semiconductor spin qubits are emerging as a leading platform for quantum computing, offering a clear pathway toward scalability. Among them, the exchange-only (EO) qubit stands out: it encodes quantum information in three spins across three quantum dots and allows for universal, all-electrical control through exchange pulses alone. Recent hardware breakthroughs, including a demonstrated processing unit with up to 18 EO qubits, have pushed the platform into a new phase where progress depends less on individual components and more on how well the target algorithm is mapped onto the hardware. An inefficient mapping, unaware of the device’s strengths and bottlenecks, inflates interaction counts and circuit depth, which increases vulnerability to errors. The near-term connectivity of these devices is also still expected to be limited to quasi-linear chains, which makes a hardware-aware compilation approach essential.
A hardware-informed path across three stages
In the new paper, ‘From NISQ to Fault-Tolerance: Applications and Algorithmic Benchmarks for Spin Qubits’, researchers Frederik Lohof, Florian Ginzel and Wolfgang Lechner from ParityQC and the University of Innsbruck provide resource estimates for a range of applications that target different stages of hardware maturity. Key contributions of the work include:
- A natural synergy between Parity Twine and EO qubits: Parity Twine relies on chains of composite gates known as DCX gates, which the EO platform can perform directly. Compiling the Parity Twine network down to the level of elementary exchange pulses, the authors show a significant reduction in resource overhead compared to previous state-of-the-art compilation methods for both the quantum Fourier transform and the quantum approximate optimization algorithm. For the QFT, the approach asymptotically reduces the pulse count by more than 22 percent and, with parallel operation, the circuit depth by more than 50 percent over the reference implementation.
- An error detection technique native to Parity Twine: The work introduces an error detection protocol that is native to the Parity Twine network and uniquely well suited to EO qubits, which can leverage it to detect bitflip and, notably, leakage errors through postselection. While not arbitrarily scalable, the overhead stays low to moderate in the currently relevant regime, offering a bridge between algorithms on purely physical qubits and full quantum error correction.
- A perspective toward fault-tolerant quantum simulation: As a bridge to utility-scale quantum computing, the authors study digital simulation of fermionic systems, specifically the fermionic fast Fourier transform and a partially fault-tolerant simulation of a Fermi-Hubbard model. They provide detailed resource estimates, minimal code distances, and identify the scaling bottlenecks that most contribute to the overhead.
Informing future hardware design
By providing quantitative resource estimates and identifying scaling bottlenecks at each level, from NISQ benchmarks to a partially fault-tolerant regime, the work offers concrete target values for the development of future spin qubit processors. Confirms Parity Twine as a prime candidate for implementing near- and mid-term algorithms on EO qubits and highlights the importance of hardware-informed compilation and chip layout choices, showing for example that an EO qubit layout on a triangular lattice can substantially reduce the physical qubit overhead without improving operation fidelities.
Read the preprint
The preprint ‘From NISQ to Fault-Tolerance: Applications and Algorithmic Benchmarks for Spin Qubits’, authored by Frederik Lohof, Florian Ginzel, and Wolfgang Lechner is now available here.
FAQ
Recent progress has moved spin qubit hardware into a phase where overall performance depends heavily on how efficiently a target algorithm is mapped onto the device. Because near-term devices are expected to have limited, quasi-linear connectivity, a mapping that ignores the hardware’s structure inflates circuit depth and gate counts, which drives up errors. The paper provides a hardware-aware roadmap and detailed resource estimates for running quantum algorithms on exchange-only (EO) qubits across different stages of hardware maturity.
An exchange-only qubit encodes quantum information in three electron spins held in three quantum dots. It is the smallest spin qubit system in which pairwise exchange coupling alone allows for universal control, which means all gate operations can be driven electrically through short exchange pulses, without the need for magnetic field gradients. This makes the control versatile, robust, and fast relative to the qubit’s coherence times.
Parity Twine is a compilation method that implements certain classes of quantum algorithms in a way that respects the hardware’s connectivity constraints, tracking information through the qubit array using parity labels. It relies on chains of composite gates called DCX gates. The natural fit with EO qubits comes from the fact that the EO platform can perform these DCX gates directly, which lets the compiled circuits make especially efficient use of the hardware and opens up additional room for reducing circuit depth at the pulse level.
The work covers the quantum approximate optimization algorithm (QAOA), the quantum Fourier transform (QFT), the fermionic fast Fourier transform (FFFT), and the simulation of a Fermi-Hubbard model. Compiled to the pulse level, the Parity Twine approach reduces resource overhead compared to previous state-of-the-art methods. For the QFT, for instance, it asymptotically lowers the pulse count by more than 22 percent, and with fully parallel operation the circuit depth can be reduced by more than 50 percent over the reference implementation.
The authors introduce an error detection protocol built into the Parity Twine network. By connecting the start of a Parity Twine chain to its end along a secondary route using an auxiliary qubit, bit-flip errors that occur along the chain can be detected and the affected runs discarded. A particular strength on the EO platform is that this scheme can also detect leakage errors, a characteristic error type for these qubits, with high probability. The method adds only a low to moderate overhead in the currently relevant regime.
As a bridge to utility-scale applications, the authors examine digital fermion simulation, including a partially fault-tolerant simulation of a Fermi-Hubbard model using a surface code. They estimate the minimal code distances required and relate them to a hardware-realistic error model for EO qubits. The analysis shows that while current fidelities are not yet sufficient for large-scale applications, the improved scaling of the parity approach loosens the requirements for quantum error correction, and it identifies the specific bottlenecks and improvement strategies that matter most.
The paper builds on the Parity Twine method and the broader Parity framework, which underpin the Parity Twine products. Parity Twine has previously been used to demonstrate a record-breaking process fidelity for the quantum Fourier transform on superconducting qubits and has been shown to offer a highly efficient approach to quantum optimization. This work extends that line of research to semiconductor spin qubits, providing the resource estimates needed to assess feasibility on real devices.
