First External Demonstration of Parity Twine on Quantum Hardware

27.05.2025. We’re delighted to announce a new milestone for ParityQC: the first external demonstration of Parity Twine on quantum hardware. A research team at Forschungszentrum Jülich has carried out the first external demonstration of Parity Twine – an implementation method originally developed by ParityQC for mapping quantum algorithms to hardware, with record efficiency.

The method was tested on QAOA (Quantum Approximate Optimization Algorithm) – a key algorithm for tackling combinatorial optimization problems using quantum processors. Using IBM’s Heron superconducting hardware, the team showed that Parity Twine leads to circuits with significantly fewer 2-qubit gates and reduced depth, outperforming all known transpilers – including Qiskit’s AI pass. In benchmark comparisons, Parity Twine and SWAP networks combined with initialization strategies based on simulated annealing achieved substantial improvements. For example, on a 120-qubit QAOA instance with 25% connectivity, Parity Twine encoding on a 1D qubit chain delivered an 85% reduction in circuit depth and a 28% reduction in 2-qubit gate count compared to Qiskit at its highest optimization level.

This external demonstration proves the advantage of Parity Twine for optimizing real quantum workloads on near-term hardware. Congratulations to the authors – Alejandro Montanez-Barrera, Yanjun Ji, Michael R. von Spakovsky, David E. Bernal Neira, Kristel Michielsen – for the excellent work using Parity Twine on quantum hardware.

Read the paper “Optimizing QAOA circuit transpilation with parity twine and SWAP network encodings” on arXiv.
Watch our video introduction of Parity Twine on YouTube.