Constructive plaquette compilation for the parity architecture

Constructive plaquette compilation for the parity architecture

Compilation is an important process for near-term quantum devices, where qubit numbers, connectivity and quality of operations are limited. The short decoherence time of such devices places further restrictions on the quantum circuits that can be successfully executed. Therefore, it is important to design algorithms that have an efficient mapping to the available hardware. Co-design of quantum hardware and software can be very fruitful, as hardware-specific optimizations can lead to improved algorithms and new algorithms can motivate hardware improvements.

In the paper “Constructive plaquette compilation for the parity architecture” the authors (Roeland ter Hoeven, Ben Niehoff, Sagar Kale and Wolfgang Lechner) present the first constructive compilation algorithm for the parity architecture using plaquettes for arbitrary higher-order optimization problems. 

This novel approach enables adiabatic protocols, where the plaquette layout can natively be implemented, as well as fully parallelized digital circuits. The algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added. The core idea is that each constraint, consisting of any qubits on the boundary of the rectangle and some new qubits, can be decomposed into plaquettes with a deterministic procedure using ancillas. 

Further in the paper, the authors show how to pick a valid set of constraints and how this decomposition works. They also present different methods to optimize the ancilla count, and show how to implement optimization problems with additional constraints. 

Read the paper here.

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